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| NO | SYMBOL | FUNCTION |
| 1 | GND | Ground |
| 2 | VCC | Power Supply for analog& 1/O system, VDD=2.5V~3.3V |
| 3 | SDA | SPl interface data input/output pin.The data is latched on the risingedge of the SCL signal |
| 4 | SCL | Write enable in MCU parallel interface. In SPI mode, this pin is usedas SCL |
| 5 | CS | Chip selection pin. Low-active |
| 6 | RESET | This signal will reset the device and it must be applied to properlyinitialize the chip. Signal is active low |
| 7~22 | DB15~DB0 | DB[15:0] are used as data bus |
| 23 | DE | Data enable signal for RGB interface operation |
| 24 | PCLK | Dot clock signal for RGB interface operation |
| 25 | HSYNC | Line synchronous signal for RGB interface operation |
| 26 | VSYNC | Frame synchronous signal for RGB interface operation |
| 27 | LEDA | LED anode |
| 28 | LEDK | LED Cathode |
| 29 | TP-RESET | Reserved pin.External Reset, Low is active |
| 30 | TP-INT3.0V | Reserved pin.Interrupt request to the host, or Wakeup requestfrom the host |
| 31 | TP-SDA3.0V | Reserved pin.I2C data input and output |
| 32 | TP-SCL3.0V | Reserved pin.I2C clock input |
| 33 | TP-VDD3.0V | Reserved pin.Power Supply For CTP |